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Jump Start into Verilog: Intensive half day course
course.2009-04-02.5917192786
Jump Start into Verilog: Intensive half day course
300
This is an ideal half day course (4 hours) for engineers or sutdents who want a quick start in understanding the language and get to work on their projects and assignments immediately. Students with current student ID receive special rates
This course is a quick introduction to Verilog, with focus on the basics, the theory, and the essentials of the language. Students taking this course will be able to write synthesizable code, simulate their design using testbenches. The information gained can be applied to any digital design.
Course Outline
1) Language basics.modules, data types
Lab1: Combintaional design and hierarchy.
2) Continuous assignments, and Procedural blocks in Verilog3) Continuous assignments, and Procedural blocks in Verilog
3) Testbenches
Lab2: Testbench for lab1.
Lab Description
The labs for this course provide a practical foundation for creating synthesizable RTL code. You will write, synthesize, and simulate (second lab), and implement (third lab).
Register Today
FPGA Xperts delivers public and private courses in locations throughout the world. Please contact Dr. Ghassan E. Shahine (734) 945-3504, or email at gshahine@ieee.org to schedule a course.
Who Should Attend?
– Engineers or students who wish to immediatley start coding their designs in Verilog.There are currently no items in this folder.