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Jump Start into VHDL: Intensive half day course
course.2008-10-18.4185140334
Jump Start into VHDL: Intensive half day course
300
This is an ideal half day course for engineers who want a quick start in understanding the language and get to work on their homeworks, or projects immediately.
This course is a quick introduction to the VHDL language, with focus on the basics, the theory, and the essentials of the language. Students taking this course will be able to write synthesizable code, as well as testbenches. The information gained can be applied to any digital design.
Course Outline
1) Language basics.
Lab1: Combintaional design and hierarchy.
2) Testbenches. Data objects, and data types.
Lab2: Testbench for lab1.
3) Operators, attributes, and data types.
Lab Description
The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate (second lab),
Register Today
FPGA Xperts delivers public and private courses in locations throughout the world. Please contact Dr. Ghassan E. Shahine (734) 945-3504, or email at gshahine@ieee.org to schedule a course.
Who Should Attend?
– Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs
Minimum Prerequisites
Knowledge of logic gates and the D flip flop
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