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Fundamentals of Verilog: Intensive one day Verilog course
Intensive one day Verilog course
Fundamentals of Verilog: Intensive one day Verilog course
600
This course covers the fundamentals of Verilog that are used in a real world design and development environment. Students taking this course should be able to write behavioral as well as RTL code, and have the confidence to code any design at any level of complexity. Please inquire about our discounted rates for students with current student ID.
This course is a thorough introduction to Verilog, with focus on the basics, the theory, and the essentials of the language. Students taking this course will be able to write synthesizable code, simulate their design using testbenches, and implement and verify their design on a development board. Students gain familiarity with simulations and verification of the design on a development board. The information gained can be applied to any digital design.
This one-day course provides students with little or no experience in Verilog the ability to write sound code and to learn the intricacies of the language so that they may develop their code with confidence, and pin-point coding errors with ease .
Course Outline
1) Language basics.
Lab1: Combintaional design and hierarchy.
2) Testbenches
3) Verilog Operators and expressions
Lab2: Testbench for lab1.
4) Data object, and data types.
5) Continuous assignments in Verilog
6) Behavioral Modeling in Verilog Part I
7) Behavioral Modeling in Verilog Part II
Lab3: Ram onboard verification.
The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate (second lab), and implement (third lab). The focus of the labs is to write code that will optimally infer reliable and high-performance designs.
Register Today
FPGA Xperts delivers public and private courses in locations throughout the world. Please contact Dr. Ghassan E. Shahine (734) 945-3504, or email at gshahine@ieee.org to schedule a course.
Who Should Attend?
– Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs
Minimum Prerequisites
Knowledge of logic gates and the D flip flop
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